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data sheet 1 lrs1341/LRS1342 data sheet stacked chip 16m flash memory and 2m sram features ? flash memory and sram stacked die chip scale package 72-ball csp (fbga072-p-0811) plastic package power supply: 2.7 v to 3.6 v operating temperature: -25c to +85c flash memory ? access time (max.): 100 ns ? operating current (max.): the current for f-v cc pin ? read: 25 ma (t cycle = 200 ns) ? word write: 17 ma ? block erase: 17 ma ? deep power down current (the current for f-v cc pin): 10 a (max. f-ce f-v cc - 0.2 v, f-rp -0.2 v, f-v pp 0.2 v) ? optimized array blocking architecture ? two 4k-word boot blocks ? six 4k-word parameter blocks ? thirty-one 32k-word main blocks ? top/bottom boot location versions ? extended cycling capability ? 100,000 block erase cycles ? enhanced automated suspend options ? word write suspend to read ? block erase suspend to word write ? block erase suspend to read sram ? access time (max.): 85 ns ? operating current (max.): ? 45 ma ?8 ma (t rc , t wc = 1 s) ? standby current: 45 a (max.) ? data retention current: 35 a (max.) description the lrs1341/LRS1342 is a combination memory organized as 1,048,576 16-bit flash memory and 131,072 16-bit static ram in one package. pin configuration figure 1. lrs1341/LRS1342 pin configuration a index a 11 a 15 nc nc nc a 14 a 9 1234567 a 16 dq 15 dq 14 s-v cc a 8 a 10 t 1 t 3 dq 13 dq 12 gnd t 4 f-we f-ry/ by f-rp t 2 f-wp f-v pp f-a 19 dq 11 t 5 b c d e f s-lb s-ub s-oe nc dq 9 8 dq 6 dq 10 dq 8 f-a 18 f-a 17 a 7 a 6 a 3 a 2 nc nc g h nc a 5 a 4 a 0 f-oe f-ce gnd nc nc a 12 a 13 910 s-we dq 4 s-ce 2 dq 2 dq 0 11 a 1 nc nc nc 12 dq 7 dq 5 f-v cc dq 3 dq 1 s-ce 1 nc LRS1342-1 top view 72-ball fbga note: two nc pins at the corner are connected. gnd
lrs1341/LRS1342 stacked chip (16m flash & 2m sram) 2 data sheet figure 2. lrs1341/LRS1342 block diagram LRS1342-2 16m (x16) bit flash memory 2m (x16) bit sram f-a 17 to f-a 19 f-ry/by gnd f-v cc f-v pp s-v cc dq 0 to dq 15 f-ce f-oe f-we f-rp f-wp a 0 to a 16 s-ce 1 s-ce 2 s-oe s-we s-lb s-ub
stacked chip (16m flash & 2m sram) lrs1341/LRS1342 data sheet 3 table 1. pin descriptions pin description type a 0 to a 16 address inputs (common) input f-a 17 to f-a 19 address inputs (flash) input f-ce chip enable input (flash) input s-ce 1 , s-ce 2 chip enable inputs (sram) input f-we write enable input (flash) input s-we write enable input (sram) input f-oe output enable input (flash) input s-oe output enable input (sram) input s-lb sram byte enable input (dq 0 to dq 7 ) input s-ub sram byte enable input (dq 8 to dq 15 ) input f-rp reset/power down (flash) block erase and word write: v ih or v hh read: v ih or v hh reset/power down: v il input f-wp write protect (flash) two boot blocks locked: v il (with f-rp = v hh erase of write can operate to all blocks) input f-ry/by ready/busy (flash) during an erase or write operation: v ol block erase and word write suspend: high-z deep power down: v oh output dq 0 to dq 15 data input/outputs (common) input/output f-v cc power supply (flash) power s-v cc power supply (sram) power f-v pp write, erase power supply (flash) block erase and word write: f-v pp = v pplk all blocks locked: f-v pp < v pplk power gnd ground (common) power nc no connection ? t 1 to t 5 test pins (should be open) ?
lrs1341/LRS1342 stacked chip (16m flash & 2m sram) 4 data sheet notes: 1. l = v il , h = v ih , x = h or l. refer to dc characteristics. 2. refer to the ? flash memory command definition ? section for valid d in during a write operation. 3. f-wp set to v il or v ih . 4. sram standby mode. see table 2a. 5. command writes involving block erase or word write are reliably executed when f-v pp = v pph and f-v cc = 2.7 v to 3.6 v. block erase or word write with v ih < rp < v hh produce spurious results and should not be attempted. 6. never hold f-oe low and f-we low at the same time. 7. s-lb , s-ub control mode. see table 2b. notes: 1. commands other than those shown in table are reserved by sharp for future device implementations and should not be used. 2. bus operations are defined in table 2. 3. xa = any valid address within the device; ia = identifier code address; ba = address within the block being erased; wa = address of memory location to be written; srd = data read from status register, see table 6; wd = data to be written at location wa. data is latched on the rising edge of f-we or f-ce (whichever goes high first); id = data read from identifier codes. 4. see table 4 for identifier codes. 5. see table 5 for write protection alternatives. table 2. truth table 1 flash sram f-ce f-rp f-oe f-we s-ce 1 s-ce 2 s-oe s-we s-lb s-ub dq 0 - dq-7 dq 8 - dq 15 notes read standby l h l h see note 4 xx see note 4 d out 2, 3 output disable standby l h h h x x high-z 3 write standby l h h l x x d in 2, 3, 5, 6 standby read h h x x l h l h see note 7 output disable h h x x l h h h x x high-z h h x x l h x x h h high-z write h h x x l h l l see note 7 reset/power down read x l x x l h l h output disable xlx x l h hhxx high-z x l x x l h x x h h high-z write x l x x l h l l see note 7 standby standby h h x x see note 4 xx see note 4 high-z 3 reset/power down standby x l x x x x high-z 3 table 2a. mode pins s-ce 1 s-ce 2 s-lb s-ub standby (sram) hxxx xlxx xxhh table 2b. mode (sram) pins s-lb s-ub dq 0 - dq 7 dq 8 - dq 15 read/write lld out /d in d out /d in lhd out /d in high-z hlhigh-zd out /d in table 3. command definition for flash memory 1 command bus cycles required first bus cycle second bus cycle notes operation 2 address 3 data 3 operation 2 address 3 data 3 read array/reset 1 write xa ffh read identifier codes 2 write xa 90h read ia id 4 read status register 2 write xa 70h read xa srd clear status register 1 write xa 50h block erase 2 write ba 20h write ba d0h 5 word write 2 write wa 40h or 10h write wa wd 5 block erase and word write suspend 1writexab0h 5 block erase and word write resume 1writexad0h 5
stacked chip (16m flash & 2m sram) lrs1341/LRS1342 data sheet 5 sr.7 = write state machine status (wsms) 1 = ready 0 = busy sr.6 = erase suspend status (ess) 1 = block erase suspended 0 = block erase in progress/completed sr.5 = erase status (es) 1 = error in block erasure 0 = successful block erase sr.4 = word write status (wws) 1 = error in word write 0 = successful word write sr.3 = v pp status (vpps) 1 = f-v pp low detect, operation abort 0 = f-v pp okay sr.2 = word write suspend status (wwss) 1 = word write suspended 0 = word write in progress/completed sr.1 = device protect status (dps) 1 = f-wp and/or f-rp lock detected, operation abort 0 = unlock sr.0 = reserved for future enhancements (r) notes: 1. check ry/by or sr.7 to determine block erase or word write completion. sr.6 - sr.0 are invalid while sr.7 = 0. 2. if both sr.5 and sr.4 are ? 1 ? s after a block erase attempt, an improper command sequence was entered. 3. sr.3 does not provide a continuous indication of f-v pp level. the wsm interrogates and indicates the f-v pp level only after block erase or word write command sequences. sr.3 is not guaranteed to report accurate feedback only when f-v pp v pph1 , v pph2 . 4. the wsm interrogates the f-wp and f-rp only after block erase or word write command sequences. it informs the system, depending on the attempted operation, if the f-wp is not v ih or f-rp is not v hh . 5. sr.0 is reserved for future use and should be masked out when polling the status register. table 4. identifier codes codes address (a 0 - a 18 ) lrs1341 data (dq 0 - dq 7 ) LRS1342 data (dq 0 - dq 7 ) manufacture code 00000h b0h b0h device code 00001h 48h 49h table 5. write protection alternatives operation f-v pp f-rp f-wp effect block erase or word write v il xx all blocks locked > v pplk v il x all blocks locked v hh x all blocks unlocked v ih v il two boot blocks locked v ih v ih all blocks unlocked table 6. status register definition wsms ess es wws vpps wwss dps r 76543210
lrs1341/LRS1342 stacked chip (16m flash & 2m sram) 6 data sheet memory maps figure 3. bottom boot for flash memory 15 [a 0 - a 19 ] f8000 fffff f7fff f0000 effff e8000 e7fff e0000 dffff d8000 d7fff d0000 cffff c8000 c7fff c0000 bffff b8000 b7fff b0000 affff a0000 9ffff a8000 a7fff 98000 97fff 90000 8ffff 88000 87fff 80000 7ffff 78000 77fff 70000 6ffff 68000 67fff 60000 5ffff 58000 57fff 50000 4ffff 48000 47fff 40000 3ffff 38000 37fff 30000 2ffff 28000 27fff 20000 1ffff 18000 17fff 10000 0ffff 08000 07fff 14 13 12 11 10 9 8 7 6 5 4 3 2 0 32k-word main block 16 32k-word main block 17 32k-word main block 18 32k-word main block 19 32k-word main block 20 32k-word main block 21 32k-word main block 22 32k-word main block 23 32k-word main block 24 32k-word main block 25 32k-word main block 26 32k-word main block 27 32k-word main block 28 32k-word main block 29 32k-word main block 30 32k-word main block 32k-word main block 32k-word main block 32k-word main block 32k-word main block 32k-word main block 32k-word main block 32k-word main block 32k-word main block 32k-word main block 32k-word main block 32k-word main block 32k-word main block 32k-word main block 1 32k-word main block 32k-word main block 07000 06fff 06000 05fff 05000 04fff 04000 03fff 03000 02fff 02000 01fff 01000 00fff 00000 5 4 3 2 1 0 0 4k-word parameter boot block 4k-word parameter boot block 4k-word parameter boot block 4k-word parameter boot block 4k-word parameter boot block 4k-word parameter boot block 1 4k-word boot block 4k-word boot block bottom boot LRS1342-3 figure 4. top boot for flash memory 7 [a 0 - a 19 ] f8000 fffff f7fff f0000 effff e8000 e7fff e0000 dffff d8000 d7fff d0000 cffff c8000 c7fff c0000 bffff b8000 b7fff b0000 affff a0000 9ffff a8000 a7fff 98000 97fff 90000 8ffff 88000 87fff 80000 7ffff 78000 77fff 70000 6ffff 68000 67fff 60000 5ffff 58000 57fff 50000 4ffff 48000 47fff 40000 3ffff 38000 37fff 30000 2ffff 28000 27fff 20000 1ffff 18000 17fff 10000 0ffff 08000 07fff 8 9 10 11 12 13 14 15 16 17 18 19 20 22 32k-word main block 6 32k-word main block 5 32k-word main block 4 32k-word main block 3 32k-word main block 2 32k-word main block 1 32k-word main block 0 32k-word main block 5 32k-word main block 4 32k-word main block 3 32k-word main block 2 32k-word main block 1 32k-word main block 0 32k-word main block 1 32k-word main block 0 32k-word main block 32k-word main block 32k-word main block 32k-word main block 32k-word main block 32k-word main block 32k-word main block 32k-word main block 32k-word main block 32k-word main block 32k-word main block 32k-word main block 32k-word main block 32k-word main block 21 32k-word main block 32k-word main block 07000 06fff 06000 05fff 05000 04fff 04000 03fff 03000 02fff 02000 01fff 01000 00fff 00000 23 24 25 26 27 28 30 4k-word parameter boot block 4k-word parameter boot block 4k-word parameter boot block 4k-word parameter boot block 4k-word parameter boot block 4k-word parameter boot block 29 4k-word boot block 4k-word boot block top boot LRS1342-13
stacked chip (16m flash & 2m sram) lrs1341/LRS1342 data sheet 7 absolute maximum ratings notes: 1. the maximum applicable voltage on any pins with respect to gnd. 2. except f-v pp . 3. except f-rp . 4. -2.0 v undershoot is allowed when the pulse width is less than 20 ns. 5. +14.0 v overshoot is allowed when the pulse width is less than 20 ns. recommended dc operating conditions t a = -25 c to +85 c notes: 1. v cc is the lower one of s-v cc and f-v cc . 2. -2.0 v undershoot is allowed when the pulse width is less than 20 ns. 3. this voltage is applicable to f-rp pin only. pin capacitance t a = 25 c, f = 1 mhz note: * sampled by not 100% tested. parameter symbol ratings unit notes supply voltage v cc -0.2 to +3.9 v 1, 2 input voltage v in -0.2 to v cc +0.3 v 1, 3, 4 operating temperature t opr -25 to +85 c storage temperature t stg -55 to +125 c f-v pp voltage f-v pp -0.2 to +14.0 v 1, 4, 5 f-rp voltage f-rp -0.5 to +14.0 v 1, 4, 5 parameter symbol min. typ. max. unit notes supply voltage v cc 2.7 3.0 3.6 v input voltage v ih 2.2 v cc + 0.2 v 1 v il -0.2 0.6 v 2 v hh 11.4 12.6 v 3 parameter symbol condition min. typ. max. unit input capacitance* c in v in = 0 v 20 pf i/o capacitance* c i/o v i/o = 0 v 22 pf
lrs1341/LRS1342 stacked chip (16m flash & 2m sram) 8 data sheet dc characteristics t a = -25 c to + 85 c, v cc = 2.7 v to 3.6 v notes: 1. reference values at v cc = 3.0 v and t a = +25 c. 2. includes f-ry/by . 3. automatic power savings (aps) for flash memory reduces typi- cal i ccr to 3 ma at 2.7 v cc in static operation. 4. cmos inputs are either v cc 0.2 v or gnd 0.2 v. ttl inputs are either v il or v ih . 5. block erases and word writes are inhibited when f-v pp v pplk and not guaranteed in the range between v pplk (max.) and v pph (min.), and above v pph (max.). 6. f-rp connection to a v hh supply is allowed for a maximum cumu- lative period of 80 hours. parameter symbol condition min. typ. 1 max. unit notes input leakage current i li v in = v cc or gnd -1.5 +1.5 a output leakage current i lo v out = v cc or gnd -1.5 +1.5 a f-v cc standby current i ccs f-ce = f-rp = f-v cc 0.2 v f-wp = f-v cc 0.2 v or f-gnd 0.2 v 25 50 a 2 f-ce = f-rp = v ih, f-wp = v ih or v il 0.2 2 ma deep power-down current i ccd f-rp = f-gnd 0.2 v, i out (f-ry/by ) = 0 ma 510a read current i ccr cmos input, f-ce = f-gnd, f = 5 mhz, i out = 0 ma 25 ma 3, 4 ttl input, f-ce = f-gnd, f = 5 mhz, i out = 0 ma 30 ma 3, 4 word write current i ccw f-v pp = 2.7 v to 3.6 v 17 ma f-v pp = 11.4 v to 12.6 v 12 ma block erase current i cce f-v pp = 2.7 v to 3.6 v 17 ma f-v pp = 11.4 v to 12.6 v 12 ma word write block erase suspend current i ccws i cces f-ce = v ih 6ma f-v pp standby or read current i pps i ppr f-v pp = f-v cc 2 15 a f-v pp > f-v cc 10 200 a deep power-down current i ppd f-rp = f-gnd 0.2 v 0.1 5 a word write current i ppw f-v pp = 2.7 v to 3.6 v 12 40 ma f-v pp = 11.4 v to 12.6 v 30 ma block erase current i ppe f-v pp = 2.7 v to 3.6 v 8 25 ma f-v pp = 11.4 v to 12.6 v 20 ma word write or block erase suspend current i ppws i ppes f-v pp = v pph 10 200 a s-v cc standby current i sb s-ce 1 , s-ce 2 s-v cc - 0.2 v or s-ce 2 0.2 v 45 a i sb1 s-ce 1 = v ih or s-ce 2 = v il 3ma operation current i cc1 s-ce 1 = v il , s-ce 2 = v ih , v in = v il or v ih , t cycle = min., i i/o = 0 ma 45 ma i cc2 s-ce 1 = 0.2 v, s-ce 2 = s-v cc - 0.2 v, v in = s-v cc - 0.2 v, or 0.2 v t cycle = 1 s, i i/o = 0 ma 8ma input low voltage v il -0.2 0.6 v input high voltage v ih 2.2 v cc + 0.2 v output low voltage v ol i ol = 0.5 ma 0.4 v 2 output high voltage (cmos) v oh1 i oh = -0.5 ma 2.2 v 2 f-v pp lockout during normal operations v pplk 1.5 v 5 f-v pp word write or block erase operations v pph1 2.7 3.6 v v pph2 11.4 12.6 v f-v cc lockout voltage v lko 1.5 v f-rp unlock voltage v hh unavailable f-wp 11.4 12.6 v 6
stacked chip (16m flash & 2m sram) lrs1341/LRS1342 data sheet 9 flash memory ac characteristics ac test conditions read cycle t a = -25 c to +85 c, v cc = 2.7 v to 3.6 v note: *f-oe may be delayed up to t elqv - t glqv after the falling edge of f-ce without impact on t elqv . parameter condition input pulse level 0 v to 2.7 v input rise and fall time 10 ns input and output timing reference level 1.35 v output load 1ttl + c l (30 pf) parameter symbol min. max. unit read cycle time t avav 100 ns address to output delay t avqv 100 ns f-ce to output delay* t elqv 100 ns f-rp high to output delay t phqv 10 s f-oe to output delay* t glqv 45 ns f-ce to output in low-z t elqx 0ns f-ce high to output in high-z t ehqz 45 ns f-oe to output in low z t glqx 0ns f-oe high to output in high-z t ghqz 20 ns output hold from address, f-ce or f-oe change, whichever occurs first t oh 0ns
lrs1341/LRS1342 stacked chip (16m flash & 2m sram) 10 data sheet write cycle (f-we controlled) 1 t a = -25 c to +85 c, v cc = 2.7 v to 3.6 v notes: 1. read timing characteristics during block erase and word write operations are the same as during read-only operations. refer to ac characteristics for read cycle. 2. refer to the ? flash memory command definition ? section for valid a in and d in for block erase or word write. parameter symbol min. max. unit write cycle time t avav 100 ns f-rp high recovery to f-we going to low t phwl 10 s f-ce setup to f-we going low t elwl 0ns f-we pulse width t wlwh 50 ns f-rp v hh setup to f-we going high t phhwh 100 ns f-wp v ih setup to f-we going high t shwh 100 ns f-v pp setup to f-we going high t vpwh 100 ns address setup to f-we going high 2 t avwh 50 ns data setup to f-we going high 2 t dvwh 50 ns data hold from f-we high t whdx 0ns address hold from f-we high t whax 0ns f-ce hold from f-we high t wheh 0ns f-we pulse width high t whwl 30 ns f-we high to f-ry/by going low t whrl 100 ns write recovery before read t whgl 0ns f-v pp hold from valid srd, f-ry/by high-z t qvvl 0ns f-rp v hh hold from valid srd, f-ry/by high-z t qvph 0ns f-wp v ih hold from valid srd, f-ry/by high t qvsl 0ns
stacked chip (16m flash & 2m sram) lrs1341/LRS1342 data sheet 11 write cycle (f-ce controlled) 1 t a = -25 c to +85 c, v cc = 2.7 v to 3.6 v notes: 1. read timing characteristics during block erase and word write operations are the same as during read-only operations. refer to ac characteristics for read cycle. 2. refer to the ? flash memory command definition ? section for valid a in and d in for block erase or word write. block erase and word write performance t a = -25 c to +85 c, v cc = 2.7 v to 3.6 v notes: 1. reference values at t a = +25 c and v cc = 3.0 v, v pp = 3.0 v. 2. excludes system-level overhead. parameter symbol min. max. unit write cycle time t avav 100 ns f-rp high recovery to f-ce going to low t phel 10 s f-we setup to f-ce going low t wlel 0ns f-ce pulse width t eleh 70 ns f-rp v hh setup to f-ce going high t pheh 100 ns f-wp v ih setup to f-ce going high t sheh 100 ns f-v pp setup to f-ce going high t vpeh 100 ns address setup to f-ce going high 2 t aveh 50 ns data setup to f-ce going high 2 t dveh 50 ns data hold from f-ce high t ehdx 0ns address hold from f-ce high t ehax 0ns f-we hold from f-ce high t ehwh 0ns f-ce pulse width high t ehel 25 ns f-ce high to f-ry/by going low t ehrl 100 ns write recovery before read t ehgl 0ns f-v pp hold from valid srd, f-ry/by high-z t qvvl 0ns f-rp v hh hold from valid srd, f-ry/by high-z t qvph 0ns f-wp v ih hold from valid srd, f-ry/by high t qvsl 0ns symbol parameter v pp = 2.7 v to 3.6 v v pp = 11.4 v to 12.6 v unit notes min. typ. 1 max. min. typ. 1 max. t whqv1 t ehqv1 word write time 32k-word block 55 15 s 2 word write time 4k-word block 60 30 s 2 block write time 32k-word block 1.8 0.6 s 2 block write time 4k-word block 0.3 0.2 s 2 t whqv2 t ehqv2 block erase time 32k-word block 1.2 0.7 s 2 block erase time 4k-word bock 0.5 0.5 s 2 t whrz1 t ehrz1 word write suspend latency time to read 7.5 8.6 6.5 7.5 s t whrz2 t ehrz2 erase suspend latency time to read 19.3 23.6 11.8 15 s
lrs1341/LRS1342 stacked chip (16m flash & 2m sram) 12 data sheet flash memory ac characteristics timing diagrams figure 5. read cycle timing diagram t avav t glqv t elqv t glqx t elqx t avqv t phqv t ehqz t ghqz t oh high z high z valid output data valid address stable standby address f-ce device address selection f-oe f-we dq f-v cc f-rp LRS1342-4
stacked chip (16m flash & 2m sram) lrs1341/LRS1342 data sheet 13 figure 6. write cycle timing diagram (f-we controlled) LRS1342-5 t avav a in a in address t avwh t whwl t whgl t whax t wlwh t elwl t wheh t whdx t ehrl t whqv1, 2, 3, 4 v pph f-v pp f-rp v pplk v il v hh v ih v il t shwh t qvsl t vpwh t phwl t dvwh d in d in data valid srd high-z d in t qvvl f-wp f-ry/by dq f-we f-oe f-ce 2 1 3 4 5 6 notes: 1. v cc power-up and standby. 2. write block erase or word write setup. 3. write block erase confirm or valid address and data. 4. automated erase or program delay. 5. read status register data. 6. write read array command. t phhwh t qvph
lrs1341/LRS1342 stacked chip (16m flash & 2m sram) 14 data sheet figure 7. write cycle timing diagram (f-ce controlled) LRS1342-6 address v pph f-v pp f-rp v pplk v il v hh v ih v il t avav t aveh t ehgl t ehax t wlel t ehwh t ehel t eleh t dveh t phwl t ehdx t ehqv1, 2, 3, 4 f-wp f-ry/by dq f-we f-oe f-ce notes: 1. v cc power-up and standby. 2. write block erase or word write setup. 3. write block erase confirm or valid address and data. 4. automated erase or program delay. 5. read status register data. 6. write read array command. a in a in t sheh t qvsl t vpeh t ehrl t qvvl t phheh t qvph d in d in data valid srd high-z d in 2 1 3 4 5 6
stacked chip (16m flash & 2m sram) lrs1341/LRS1342 data sheet 15 reset operations t a = -25 c to +85 c, v cc = 2.7 v to 3.6 v notes: 1. if f-rp is asserted while a block erase or word write operation is not executing, the reset will complete with 100 ns. 2. a reset time t phqv is required from the later of f-ry/by going high-z, or f-rp going high until outputs are valid. 3. when the device power-up, holding f-rp low minimum 100 ns is required after v cc has been in predefined range and also has been stable there. parameter symbol min. max. unit notes f-rp pulse low time (if f-rp is tied to v cc , this specification is not applicable). t plph 100 ns f-rp low to reset during block erase or word write t plrz 23.6 s 1, 2 f-v cc 2.7 v to f-rp high t vph 100 ns 3 figure 8. ac waveform for reset operation t plph t plph high z high z f-ry/by (r) v ol v ih v il t vph t plrz a. reset during read array mode b. reset during block erase or word write c. f-rp rising timing f-rp (p) v ih v il f-rp (p) f-ry/by (r) v ol 2.7 v f-v cc v il v ih v il f-rp (p) LRS1342-7
lrs1341/LRS1342 stacked chip (16m flash & 2m sram) 16 data sheet sram ac electrical characteristics ac test conditions note: *including scope and jig capacitance. read cycle t a = -25 c to +85 c, v cc = 2.7 v to 3.6 v note: *active output to high impedance and high impedance to output active tests specified for a 200 mv transition from steady state levels into the test load. write cycle t a = -25 c to +85 c, v cc = 2.7 v to 3.6 v note: *active output to high impedance and high impedance to output active tests specified for a 200 mv transition from steady state levels into the test load. parameter condition input pulse level 0.4 v to 2.7 v input rise and fall time 5 ns input and output timing reference level 1.5 v output load* 1ttl + c l (30 pf) parameter symbol min. max. unit read cycle time t rc 85 ns address access time t aa 85 ns chip enable access time s-ce 1 t ace1 85 ns s-ce 2 t ace2 85 ns byte enable access time t be 85 ns output enable to output valid t oe 45 ns output hold from address change t oh 10 ns s-ce 1 , s-ce 2 low to output active* s-ce 1 t lz1 10 ns s-ce 2 t lz2 10 ns s-oe low to output active* t olz 10 ns s-ub or s-lb low to output in high impedance* t blz 10 ns s-ce 1 , s-ce 2 high to output in high impedance* s-ce 1 t hz1 025ns s-ce 2 t hz2 025ns s-oe high to output in high impedance* t ohz 025ns s-ub or s-lb high to output in high impedance* t bhz 025ns parameter symbol min. max. unit write cycle time t wc 85 ns chip enable to end of write t cw 75 ns address valid to end of write t aw 75 ns byte enable to end of write t bw 75 ns address setup time t as 0ns write pulse width t wp 65 ns write recovery time t wr 0ns input data setup time t dw 35 ns input data hold time t dh 0ns s-we high to output active* t ow 5ns s-we low to output in high impedance* t wz 025ns
stacked chip (16m flash & 2m sram) lrs1341/LRS1342 data sheet 17 sram ac characteristics timing diagrams figure 9. read cycle timing diagram t rc t aa t ace1, 2 t lz t hz t hz t bhz t ohz data valid t oh t blz t olz d out t oe t be address s-ce 1 s-ce 2 s-ub, s-lb s-oe LRS1342-8 note: s-we is high for read cycle.
lrs1341/LRS1342 stacked chip (16m flash & 2m sram) 18 data sheet figure 10. write cycle timing diagram (s-we controlled) t wc t aw t cw t bw t wp t wr t as t wz t ow t dh t dw t wr (note 2) (note 3) (note 7) (note 5) (note 4) (note 8) (note 6) d out d in address s-ce 1 s-ce 2 s-ub, s-lb s-we data valid LRS1342-9 notes: 1. a write occurs during the overlap of a low s-ce 1 , a high s-ce 2 and a low s-we. a write begins at the latest transition among s-ce 1 going low, s-ce 2 going high and s-we going low. a write ends at the earliest transition among s-ce 1 going high, s-ce 2 going low and s-we going high. t wp is measured from the beginning of write to the end of write. 2. t cw is measured from the later of s-ce 1 going low or s-ce 2 going high to the end of write. 3. t bw is measured from the time of going low s-ub or low s-lb to the end of write. 4. t as is measured from the address valid to the beginning of write. 5. t wr is measured from the end of write to the address change. 6. during this period, dq pins are in the output state, therefore the input signals of opposite phase to the outputs must not be applied. 7. if s-ce 1 goes low or s-ce 2 goes high simultaneously with s-we going low or after s-we going low, the outputs remain in high impedance state. 8. if s-ce 1 goes high or s-ce 2 goes low simultaneously with s-we going high or s-we going high, the outputs remain in high impedance state.
stacked chip (16m flash & 2m sram) lrs1341/LRS1342 data sheet 19 figure 11. write cycle timing diagram (s-ce controlled) t wc t aw t cw t as (note 2) (note 4) (note 3) (note 7) (note 6) t wr t wr t dw t dh t bw t wp high impedance (note 5) d out d in address s-ce 1 s-ce 2 s-ub, s-lb s-we data valid LRS1342-10 notes: 1. a write occurs during the overlap of a low s-ce 1 , a high s-ce 2 and a low s-we. a write begins at the latest transition among s-ce 1 going low, s-ce 2 going high and s-we going low. a write ends at the earliest transition among s-ce 1 going high, s-ce 2 going low and s-we going high. t wp is measured from the beginning of write to the end of write. 2. t cw is measured from the later of s-ce 1 going low or s-ce 2 going high to the end of write. 3. t bw is measured from the time of going low s-ub or low s-lb to the end of write. 4. t as is measured from the address valid to the beginning of write. 5. t wr is measured from the end of write to the address change. 6. during this period, dq pins are in the output state, therefore the input signals of opposite phase to the outputs must not be applied. 7. if s-ce 1 goes low or s-ce 2 goes high simultaneously with s-we going low or after s-we going low, the outputs remain in high impedance state.
lrs1341/LRS1342 stacked chip (16m flash & 2m sram) 20 data sheet figure 12. write cycle timing (s-ub , s-lb controlled) t wc t aw t cw t bw t wp t wr t as t wz t ow t dh t dw t wr (note 2) (note 3) (note 7) (note 5) (note 4) (note 8) (note 6) d out d in address s-ce 1 s-ce 2 s-ub, s-lb s-we data valid LRS1342-11 notes: 1. a write occurs during the overlap of a low s-ce 1 , a high s-ce 2 and a low s-we. a write begins at the latest transition among s-ce 1 going low, s-ce 2 going high and s-we going low. a write ends at the earliest transition among s-ce 1 going high, s-ce 2 going low and s-we going high. t wp is measured from the beginning of write to the end of write. 2. t cw is measured from the later of s-ce 1 going low or s-ce 2 going high to the end of write. 3. t bw is measured from the time of going low s-ub or low s-lb to the end of write. 4. t as is measured from the address valid to the beginning of write. 5. t wr is measured from the end of write to the address change. 6. during this period, dq pins are in the output state, therefore the input signals of opposite phase to the outputs must not be applied. 7. if s-ce 1 goes low or s-ce 2 goes high simultaneously with s-we going low or after s-we going low, the outputs remain in high impedance state. 8. if s-ce 1 goes high or s-ce 2 goes low simultaneously with s-we going high or s-we going high, the outputs remain in high impedance state.
stacked chip (16m flash & 2m sram) lrs1341/LRS1342 data sheet 21 sram data retention characteristics t a = -25 c to +85 c notes: 1. reference value at t a = 25 c, s-v cc = 3.0 v. 2. s-ce 1 v cc - 0.2 v, s-ce 2 v cc - 0.2 v (s-ce 1 controlled) or s-ce 2 0.2 v (s-ce 2 controlled). parameter symbol conditions min. typ. 1 max. unit notes data retention supply voltage v ccdr s-ce 2 0.2 v or s-ce 1 v ccdr - 0.2 v 2.0 3.6 v 2 data retention supply current i ccdr v ccdr = 3v, s-ce 2 0.2 v or s-ce 1 v ccdr - 0.2 v 35 a 2 chip enable setup time t cdr 0ns chip enable hold time t r 5ms figure 13. data retention timing diagram (s-ce 1 controlled) figure 14. data retention timing diagram (s-ce 2 controlled) data retention mode 2.7 v 0 v note: to control the data retention mode at s-ce 1 , fix the input level of s-ce 2 between v ccdr and v ccdr - 0.2 v, or 0 v and 0.2 v, and during the data retention mode. 2.2 v v ccdr s-v cc s-ce 1 s-ce 1 v ccdr - 0.2 v t cdr t r LRS1342-12 data retention mode 0.6 v 0 v 2.7 v v ccdr s-v cc s-ce 2 s-ce 2 0.2 v t cdr t r LRS1342-13
lrs1341/LRS1342 stacked chip (16m flash & 2m sram) 22 data sheet general design guidelines supply power maximum difference (between f-v cc and s-v cc ) of the voltage is less than 0.3 v. power supply and chip enable of flash memory and sram s-ce 1 should not be low and s-ce 2 should not be high when f-ce is low simultaneously. if the two memories are active together, they may not operate normally because of interference noises or data collision on dq bus. both f-v cc and s-v cc need to be applied by the recommended supply voltage at the same time except sram data retention mode. power up sequence when turning on flash memory power supply, keep f-rp low. after f-v cc reaches over 2.7 v, keep f-rp low for more than 100 ns. device decoupling the power supply needs to be designed carefully because one of the sram and the flash memory is in standby mode when the other is active. a careful decoupling of power supplies is necessary between sram and flash memory. note peak current caused by transition of control signals (f-ce , s-ce 1 , s-ce 2 ). flash memory data protection noises having a level exceeding the limit specified in the specification may be generated under specific operating conditions on some systems. such noises, when induced onto f-we signal or power supply may be interpreted as false commands, causing undesired memory updating. to protect the data stored in the flash memory against unwanted overwriting, systems operating with the flash memory should have the following write pro- tect designs, as appropriate: protecting data in specific block by setting a f-wp to low, only the boot block can be protected against overwriting. parameter and main blocks cannot be locked. system program, etc., can be locked by storing them in the boot block. when a high voltage is applied to f-rp , overwrite operation is enabled for all blocks. for further information on setting/resetting of block bit, and controlling of f-wp and f-rp , refer to the ? command definitions ? section. data protection through f-v pp when the level of f-v pp is lower than f-v pplk (lock- out voltage), write operation on the flash memory is dis- abled. all blocks are locked and the data in the blocks are completely write protected. for the lockout voltage refer to the ? dc characteris- tics ? section. data protection during voltage transition data protection through f-rp when the f-rp is kept low during power up and power down sequence, write operation on the flash memory is disabled, write protecting all blocks. for details of f-rp control refer to the ? flash memory ac electrical characteristics ? section. design considerations power supply decoupling to avoid a bad effect on the system by flash memory power switching characteristics, each device should have a 0.1 f ceramic capacitor connected between its v cc and gnd and between its v pp and gnd. low inductance capacitors should be placed as close as possible to package leads. v pp trace on printed circuit boards updating the memory contents of flash memories that reside in the target system requires that the printed circuit board designer pay attention to the v pp power supply trace. use similar trace widths and layout con- siderations given to the v cc power bus. the inhibition of overwrite operation please do not execute reprogramming ? 0 ? for the bit which has already been programmed ? 0 ? . overwrite operation may generate unerasable bit. in case of reprogramming ? 0 ? to the data which has been pro- grammed ? 1 ? . program ? 0 ? for the bit in which you want to change data from ? 1 ? to ? 0 ? . program ? 1 ? for the bit which has already been pro- grammed ? 0 ? . for example, changing data from ? 1011110110111101 ? to ? 1010110110111100 ? requires ? 1110111111111110 ? programming. power supply block erase, full chip erase, word write and lock-bit configuration with an invalid v pp (see ? dc characteris- tics ? ) produce spurious results and should not be attempted. device operations at invalid v cc voltage product spurious results and should be attempted.
stacked chip (16m flash & 2m sram) lrs1341/LRS1342 data sheet 23 outline dimensions fbga072-p-0811 detail 0.10 s (see detail) +0.2 -0 1.4 max. 0.4 typ. 1.2 typ. 0.8 typ. 0.4 typ. 0.8 typ. 1.1 typ. h g f e d c b a 12345678 9101112 0.45 0.05 0.35 0.05 0.40 typ. 0.30 0.15 m index 0.10 s s note: dimensions are in mm. 72fbga m s s ab cd 11.0 +0.2 -0 8.0 top view side view c d bottom view b a
lrs1341/LRS1342 stacked chip (16m flash & 2m sram) ?1999 by sharp corporation reference code sma99092 north america europe asia sharp microelectronics of the americas 5700 nw pacific rim blvd. camas, wa 98607, u.s.a. phone: (360) 834-2500 telex: 49608472 (sharpcam) facsimile: (360) 834-8903 http://www.sharpsma.com sharp electronics (europe) gmbh microelectronics division sonninstra ? e 3 20097 hamburg, germany phone: (49) 40 2376-2286 facsimile: (49) 40 2376-2232 http://www.sharpmed.com life support policy sharp components should not be used in medical devices with life support functions or in safety equipment (or similiar applicat ions where component failure would result in loss of life or physical harm) without the written approval of an officer of the sharp corpor ation. limited warranty sharp warrants to its customer that the products will be free from defects in material and workmanship under normal use and ser vice for a period of one year from the date of invoice. customer's exclusive remedy for breach of this warranty is that sharp will either (i) repair or replace, at its option, any product which fails during the warranty period because of such defect (if customer promptly reporte d the failure to sharp in writing) or, (ii) if sharp is unable to repair or replace, refund the purchase price of the product upon its return to sharp. this warranty does not apply to any product which has been subjected to misuse, abnormal service or handling, or which has been alte red or modified in design or construction, or which has been serviced or repaired by anyone other than sharp. the warranties set forth herein are in lieu of, and exclusive of, all other warranties, express or implied. all express and implied warranties, including the warranties of merchantability, fitness for use and fitness for a particular purpose, are specifically excluded. in no event will sharp be liable, or in any way responsible, for any incidental or consequential economic or property damage. the above warranty is also extended to customers of sharp authorized distributors with the following exception: reports of fail ures of products during the warranty period and return of products that were purchased from an authorized distributor must be made through the d istributor. in case sharp is unable to repair or replace such products, refunds will be issued to the distributor in the amount of distribu tor cost. sharp reserves the right to make changes in specifications at any time and without notice. sharp does not assume any responsibi lity for the use of any circuitry described; no circuit patent licenses are implied. sharp corporation integrated circuits group 2613-1 ichinomoto-cho tenri-city, nara, 632, japan phone: +81-743-65-1321 facsimile: +81-743-65-1532 http://www.sharp.co.jp

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